Welcome to my homepage. My name is Lei Zhao.

I got my Ph.D. from University of Pittsburgh in 2022. I received my B.S. degree of Software Engineering in 2011 and M.S. degree of Computer Science in 2014 respectively from Northwestern Polytechnical University in China. After graduation, I worked as a postdoctoral research scientist in Meta Reality Labs from 2022 to 2023. Starting from 2023, I joined Artificial Intelligence Research Lab in HPE.

CV Dissertation(PDF) Dissertation(slides)

Research

I specialize in the design and optimization of neural network accelerators, spanning architecture, compiler, and system levels. My expertise includes MLIR-based compiler development, accelerator simulation and performance analysis, and hardware–software co-design for efficient deep learning execution. While I have extensive experience in in-memory computing and emerging memory technologies, my broader focus is on advancing AI hardware architectures and compiler frameworks for next-generation machine learning systems.

Although my recent projects involve in-memory and analog computing, my primary expertise is in computer architecture and system design. I leverage existing compute units to build complete accelerators, compiler toolchains, and model optimization frameworks—an approach that readily generalizes to any hardware architecture or technology.

Publications

Full publication list is at HERE.

RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
Lei Zhao, Aishwarya Natarajan, Luca Buonanno, Archit Gajjar, Ron Roth, Sergey Serebryakov, John Moon, Omar Eldash, Jim Ignowski and Giacomo Pedretti
International Conference on Computer Design (ICCD), 2025.
[Paper] [Slides]

Optical content-addressable memories for tree-based machine learning
London, Yanir, Luca Buonanno, Lei Zhao, Giacomo Pedretti, Bassem Tossoun, Stanley Cheung, Yuan Yuan, Yiwei Peng, Matej Hejda and Marco Fiorentino
AI and Optical Data Sciences VI, 2025.
[Paper] [Slides]

Analog In-memory Computing Enhanced FPGA for HighThroughput and Energy-Efficient Acceleration
Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski, Aman Aro and Luca Buonanno
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025.
[Paper] [Slides]

Enhancing FPGAs with Analog In-Memory Computing Macros
Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Rand Jean, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski and Luca Buonanno
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (ISFPGA), 2025.
[Paper] [Slides]

Noise Aware Finetuning for Analog Non-Linear Dot Product Engine
Lei Zhao, Luca Buonanno, Aishwarya Natarajan, Jim Ignowski and Giacomo Pedretti
ML with New Compute Paradigms (MLNCP) at NeurIPS (MLNCP workshop at NeurIPS), 2024.
[Paper] [Slides]

Memristive Quaternary Content-Addressable Memories for Implementing Boolean Functions
Luca Buonanno, Giacomo Pedretti, Lei Zhao, Aishwarya Natarajan, Todd Richmond, John Moon, Rand Jean, Xia Sheng, Ron Roth and Jim Ignowski
IEEE International Symposium on Circuits and Systems (ISCAS), 2024.
[Paper] [Slides]

ReARVR: A ReRAM-Based DNN Accelerator for Mobile Devices
Lei Zhao, Yuecheng Li, Jae-sun Seo, H. Ekin Sumbul, Edith Beigne, and Dawei Wang
Design Automation Conference (Poster Session) (DAC), 2023.
[Paper] [Slides]

A DNN Protection Solution for PIM Accelerators With Model Compression
Lei Zhao, Youtao Zhang, and Jun Yang
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022.
[Paper] [Slides]

SRA: A Secure ReRAM-Based DNN Accelerator
Lei Zhao, Youtao Zhang, and Jun Yang
Design Automation Conference (DAC), 2022.
[Paper] [Slides]

Flipping Bits to Share Crossbars in ReRAM-Based DNN Accelerator
Lei Zhao, Youtao Zhang, and Jun Yang
International Conference on Computer Design (ICCD), 2021.
Best paper candidate
[Paper] [Slides]

SCA: A Secure CNN Accelerator for both Training and Inference
Lei Zhao, Youtao Zhang, and Jun Yang
Design Automation Conference (DAC), 2020.
[Paper] [Slides]

RFAcc: A 3D ReRAM Associative Array based Random Forest Accelerator
Lei Zhao, Quan Deng, Youtao Zhang, and Jun Yang
International Conference on Supercomputing (ICS), 2019.
[Paper] [Slides]

AEP: An Error-bearing Neural Network Accelerator for Energy Efficiency and Model Protection
Lei Zhao, Youtao Zhang, and Jun Yang
International Conference On Computer Aided Design (ICCAD), 2017.
[Paper] [Slides]

Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns
Wen Wen, Lei Zhao, Youtao Zhang, and Jun Yang
International Conference On Computer Aided Design (ICCAD), 2017.
[Paper]

Mitigating Shift-Based Covert-Channel Attacks in Racetrack Last Level Caches
Lei Zhao, Youtao Zhang, and Jun Yang
Non-Volatile Memory Systems and Applications Symposium (NVMSA), 2017.
[Paper] [Slides]

Constructing Fast and Energy Efficient 1TnR based ReRAM Crossbar Memory
Lei Zhao, Lei Jiang, Youtao Zhang, Nong Xiao, and Jun Yang
International Symposium on Quality Electronic Design (ISQED), 2017.
Best paper candidate
[Paper] [Slides]

Exploit Common Source-Line to Construct Energy Efficient Domain Wall Memory based Caches
Xianwei Zhang, Lei Zhao, Youtao Zhang, and Jun Yang
International Conference on Computer Design (ICCD), 2015.
[Paper]

Privacy-preserving Time Series Medical Images Analysis Using a Hybrid Deep Learning Framework
Zijie Yue, Shuai Ding, Lei Zhao, Youtao Zhang, Zehong Cao, M. Tanveer, Alireza Jolfaei and Xi Zheng
ACM Transactions on Internet Technology, 2020.
[Paper]

Exploiting In-memory Data Patterns for Performance Improvement on Crossbar Resistive Memory
Wen Wen, Lei Zhao, Youtao Zhang, and Jun Yang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
[Paper]

Contact Me

3404 E Harmony Rd
Hewlett Packard Enterprise
Fort Collins, CO 80528, USA
E-mail: lei.zhao@hpe.com